The present invention relates to a thin film semiconductor device and a semiconductor substrate sheet to be used in the semiconductor device as well as a method for producing them.
As is well known, a thin film semiconductor device also known as a thin film transistor (TFT) device) is formed on a semiconductor substrate, which typically consists of a thin film layer of semiconductor material, such as silicon, over a base layer of insulation material, such as non-alkaline glass, or quarts glass. In the thin film layer of the semiconductor, a plurality of channels interposed between of a source area and a drain area are formed, and each of channels is equipped with a gate electrode separated by an insulation film from the above areas.
FIGS. 4(a) to 4(e) show a typical conventional process for producing a TFT, which includes the following steps. Those steps are forming a thin film layer (202) of non-single-crystalline semiconductor material such as silicon over the base layer (201) of insulation material such as glass as shown in FIG. 4(a), crystallizing the semiconductor layer (202) by irradiation of energy beam (203) such as excimer laser as shown in FIG. 4(b), processing the crystallized semiconductor layer (204) to form an “island” (205) and forming a gate insulation film (206) of insulation material such as silicon oxide (SiO2) as shown in FIG. 4(c), forming a gate electrode (207) on the gate insulation film and implanting impurity ion (208) such as phosphorous ion into the crystallized semiconductor layer (204) by using the gate electrode (207) as the implantation mask as shown in FIG. 4(d), and forming an activated source area (209) and a drain area (210) as well as a channel area (211) interposed therebetween, forming contact holes upon the source area and the drain area, and forming a source electrode (212) and a drain electrode(213) as shown in FIG. 4(e).
One of disadvantages of the above typical conventional process is that the grain size of crystallized semiconductor becomes variant and, as the result thereof, the number of grain boundaries crossing a channel area becomes also variant at every one-unit channel areas.
Such variance of the number of grain boundaries crossing each channel area tends to cause the variance of characteristics of each TFT such as mobility and operation threshold voltage. When representing the channel length by “Lg” and representing the gran size by “φ”, it is possible to make the variance of TFT characteristics to be not so noticeable in the case of “φ/Lg<<1”. However, the variance of TFT characteristics become noticeable according to the increase of “φ/Lg” in case of “φ/Lg>⅕”. For instance, in case of producing a standard size TFT having a channel size of about 5μ×5μ, when a polysilicon thin film consisting of crystal grains having such variance of grain size as from 1 μm to several tens micron millimeters, the number of grain boundaries running in the source/drain direction vary in the order of “0˜5”, which causes inevitably a noticeable variance of TFT characteristics.
Furthermore, a semiconductor thin film produced by the foregoing conventional process, it is inevitable that a mountain-shaped projection is formed at the triple-contact point of grain boundaries owing to the crystallization by annealing with laser irradiation. The height of such projection may be 30˜80 nm in case of forming a polysilion thin film of 50 nm thickness. The existence of such projection tends to make the interface between the gate insulation film and the semiconductor film to be uneven, which in turn tends to cause the degradation of mobility due to scattering of careers at the interface or to cause performance degradation due to the concentration of electric field at the end.
One possible way for avoiding the above disadvantages is to increase the thickness of the gate insulation film to the degree of about 100 nm. But, this way may cause to degrade the level of ON-state electric current. The increase of thickness may further cause to make the activation rate by implantation of impurities to source/drain area to be variant, which in turn causes the variance of electrode resistance, owing to the segregation of atoms of impurities to the grain boundaries.
Many trials have been made for the purpose of increasing of grain size or avoiding variance of grain size, without changing the order of steps in the foregoing conventional process. For instance, the inventors of the present invention have proposed a new method for producing a thin film semiconductor device by the U.S. patent application Ser. No. 10/19285, in which it is proposed to carry out the irradiation of energy beam in a distribution of irradiation strength in such manner as decreasing the beam strength successively from the maximum to the minimum in a predetermined area, thereby to obtain a thin film semiconductor device having crystal grains of even size in a regulated configuration is obtained.
The inventors of the present invention have intended to develop a new process, which, without being confined to the order of steps in the conventional process, makes it possible to obtain a thin film semiconductor device in which large size crystal grains are arranged regulatedly at the position corresponding to every unit channels.